Arm Cortex processor behaviors Community

Prerequisites: * Introductory knowledge of either the A, R, or M profile of the Arm architecture. AUDIENCE: The course is aimed at Hardware Engineers needing an understanding processor signal behaviors. The course will also benefit software and implementation engineers. DELIVERY METHOD: * Online LENGTH: * 1 hour MODULES: * INTRODUCTION * Topic overview * Simple Sequential Model * INSTRUCTION FETCHING OPTIMIZATIONS  * Intro to instruction fetching optimizations * Branch prediction overview * Branch prediction method (return stack) * Branch prediction method (conditional branch prediction) * Effects of branch prediction * DATA PROCESSING OPTIMIZATIONS  * Data processing optimizations - overview * Multiple execution pipelines * Speculative execution * Register dependencies * Cortex-A, R, and M interrupt behaviors * DATA MEMORY ACCESS OPTIMIZATIONS * Data memory access optimizations - overview * Caching (cache eviction) * Caching (cache pre-fetching performance * Caching (cache maintenance - multi-caching) * Merging * Re-ordering overview * Re-ordering commands * ISB and DSB example * Barriers and speculative access * SUMMARY * Cortex-A summary * Cortex-R summary * Cortex-M summary LANGUAGE: This course is presented in English. DELIVERY METHOD: Bitesized video content By booking this training course you accept our Terms and Conditions [http://www.arm.com/files/pdf/LES-PRE-20934_ARM_Event_Booking_Terms-EventBrite-v0.8.pdf]. You will have 3 months access to this community.